发明名称 Semiconductor memory device with MOS transistors each having floating gate and control gate and method of controlling the same
摘要 A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, first sense amplifiers and second sense amplifiers. The memory cell array includes memory cells arranged in a matrix. The first bit line connects commonly the memory cells in a same column. The second bit line connects commonly two or more of the first bit lines. The first sense amplifier is provided for the second bit line and controls not only the connection between the second bit lines and the first bit lines but also the potential on the second bit lines according to the data read from the memory cells onto the first bit lines. The second sense amplifier precharges the first bit line via the second bit line and the first sense amplifier and, when reading the data from the memory cells, amplifies the potential on the second bit lines.
申请公布号 US2007104002(A1) 申请公布日期 2007.05.10
申请号 US20060445302 申请日期 2006.06.02
申请人 EDAHIRO TOSHIAKI 发明人 EDAHIRO TOSHIAKI
分类号 G11C7/00;G11C16/06 主分类号 G11C7/00
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