| 摘要 |
There is disclosed a duty ratio adjustment for adjusting the duty ratio of an input clock signal. First and second one-shot pulse generation circuits respectively detect rising/tailing edges of an external input signal and output pulse signals of constant widths. Third and fourth one-shot pulse generation circuits respectively detect rising/tailing edges of an output signal from the delay circuit and output pulse signals. A selector circuit outputs the pulse signals that are output from the third and second one-shot pulse generation circuits as H edge /L edge generation clock signals, when the L width is broadened, and outputs the pulse signals that are output from the first and fourth one-shot pulse generation circuits as H edge /L edge generation clock signals, when the H width is broadened. A waveform synthesis circuit outputs a signal that changes to a high level between the timing during which the high edge generation signal is output from the selector circuit and the timing during which the low edge generation signal is output from the selector circuit, as an internal clock signal.
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