发明名称 Logical circuit
摘要 A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.
申请公布号 US2007103218(A1) 申请公布日期 2007.05.10
申请号 US20060643888 申请日期 2006.12.22
申请人 发明人 KOBAYASHI HIROYUKI;OKUDA MASAKI
分类号 H03K5/13 主分类号 H03K5/13
代理机构 代理人
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