发明名称 SENSE AMPLIFIER WITH PULL-UP CIRCUIT FOR ACCELERATED LATCHING OF LOGIC LEVEL OUTPUT DATA
摘要 PROBLEM TO BE SOLVED: To provide an amplifier circuit which maximizes the performance of the circuit. SOLUTION: A sense amplifier circuit includes a differential input circuit which receives first and second data inputs, and generates, in response to a first control signal being active LOW, a differential voltage across first and second nodes, which is indicative of a voltage difference between the first and second inputs; a pull-up circuit which connects, in response to a second control signal being active LOW, a high voltage reference to the first and second nodes; a latching circuit which generates and latches, in response to voltages provided on the first and second nodes by the differential input circuit and the pull-up circuit, first and second latched data outputs; and an equalization circuit which equalizes, in response to a third control signal being active LOW, voltages on data lines respectively connected to the first and second data outputs. The first and second control signals are set such that the second control signal is activated LOW after a finite period following the initial activation of the first control signal. The third control signal is activated LOW when the first and second control signals are inactive HIGH. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007116722(A) 申请公布日期 2007.05.10
申请号 JP20060307283 申请日期 2006.11.13
申请人 CIRRUS LOGIC INC 发明人 DU HE;WANG YUN-TI
分类号 G11C11/419;H03K19/0185;G11C7/06;H03K19/096 主分类号 G11C11/419
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