发明名称 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To improve destructive resistance with a parasitic npn transistor of IGBT. SOLUTION: A part of a source electrodes 18 is brought into contact only with a p-type high concentration well layer 13 via a contact hole 21. Another part is brought into contact only with a source layer 12 via the contact hole 21. By this way, in the inside of a p-type well layer 14 formed between adjacent gate electrodes 11 in a straight-line shape, a p-type high concentration well layer 13 is formed in a shape of a straight line. Accordingly, the resistance component of the p-type well layer 14 is made small so that the parasitic npn bipolar transistor in IGBT may be prevented from turning on, and thus, the destructive resistance is improved. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007115802(A) 申请公布日期 2007.05.10
申请号 JP20050303990 申请日期 2005.10.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OTA TOMONARI;HASHIZUME SHINGO;OOTSUJI MICHIYA
分类号 H01L29/78;H01L21/336;H01L29/739 主分类号 H01L29/78
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