| 摘要 |
PROBLEM TO BE SOLVED: To prevent the deterioration of conversion precision in a successive comparison type ADC used for a wide dynamic range. SOLUTION: A correction capacitor 14 whose static capacitance is C/2<SP>x</SP>(wherein x is 2 or 3) is connected via a switch 15 between an internal node N and a line of a reference voltage VL, and charged up to a voltage VL-VT (wherein VT is a threshold voltage of an inverter 21) in a hold operation state. Variations in an internal voltage VN of the internal node N are suppressed by turning on the switch 15 in a comparison operation of the MSB. The switch 15 is turned off to disconnect the correction capacitor 14 in comparison operations of second and succeeding bits. After the comparison up to the LSB is finished, a correction amount of 2<SP>x</SP>is added to switching signals S1 to Sn and a digital output signal DO is obtained. COPYRIGHT: (C)2007,JPO&INPIT
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