| 摘要 |
PROBLEM TO BE SOLVED: To automatically generate an assertion even with respect to a circuit for which detailed specifications or circuit descriptions cannot be analyzed. SOLUTION: An automatic signal change information generation part 103 generates pieces of signal change information 104 and 105 for a verification object signal and a verification reference signal, corresponding to the verification object signal respectively from signal information 101, which is the information of the signal name in a verification object circuit and a verification reference circuit respectively and operation waveform data 102, which is the information indicating the level transition of signals appearing in the evaluation pattern of the verification object circuit within the operation pattern of the verification reference circuit. An assertion generation part 106 inputs signal change information and generates the assertion 107, which is a description expressing the functional specifications and the design intention of a logic circuit. COPYRIGHT: (C)2007,JPO&INPIT
|
