| 摘要 |
A nanocrystal memory element and a method for fabricating the same involves repeatedly and alternately depositing, by atomic layer deposition, conductive layers and dielectric layers on a substrate with a tunnel oxide layer formed thereon, forming multiple layers of nanocrystal groups as a result of crystallization of conductive layers in a rapid thermal annealing process, and forming a gate on the top dielectric layer. The nanocrystal groups disposed at any two neighboring levels are separated by one dielectric layer, thus a plurality of nanocrystals formed in an integration layer are disposed at the same level. Barrier widths between a channel and the nanocrystals of the nanocrystal groups disposed at the same level are equal. Therefore, the nanocrystals at the same level are subjected the same electric field when voltage is applied to the gate, resulting in improved transistor performance, enhanced control of threshold voltage, and avoidance of over-erasing.
|
