DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit design capable of suppressing increase in the number of lines and the total area of cells while avoiding a wiring congestion in a layout process. SOLUTION: A logic synthesis process for forming a netlist used for a layout comprises: a step S3 of grouping netlists formed without setting use restriction and prohibition of a cell assumed to cause wiring congestion; a step S6 of determining wiring congestion for each group; a step S7 of estimating a cell which causes wiring congestion for each group determined to cause wiring congestion by the determination of wiring congestion and forming a netlist again while prohibiting use of the causal cell, thereby avoiding wiring congestion on the layout; and a step S7a of padding the circumference of the causal cell, thereby avoiding the wiring congestion on the layout. COPYRIGHT: (C)2007,JPO&INPIT