| 摘要 |
PROBLEM TO BE SOLVED: To prevent the deterioration of a cache hit rate when an arithmetic processing unit configured as a multi-processor is used as a single processor. SOLUTION: A cache access transmission means 132 outputs an access address acquired through a local cache access address input means 161 from a CPU 110 through a remote cache access address output means 164 to a shared address bus 81. A cache access control means 231 performs access to a cache memory 221 by using the access address acquired from the shared address bus 81 through a remote cache access address input means 265. That is, the access address output from the CPU 110 of the processor 100 is output from the cache access transmission means 132, and acquired by the cache access control means 231, to be available for access from a processor 200 to the cache memory 221. COPYRIGHT: (C)2007,JPO&INPIT
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