Reconfigurable signal processor architecture using multiple complex multiply-accumulate units

摘要

A reconfigurable digital signal processor (DSP) comprises: a reconfigurable data path comprising a plurality of reconfigurable multiply-accumulate (MAC) units; and a programmable finite state machine for controlling the plurality of reconfigurable MAC units. The programmable finite state machine executes a first plurality of context-related instructions that cause selected ones of the plurality of reconfigurable MAC units to perform at least one of a defined set of functions consisting essentially of: i) Fourier transform functions; and ii) filter functions. The Fourier transform functions comprise a Fast Fourier Transform (FFT) function and an Inverse Fast Fourier Transform (FFT) function and the filter functions comprise a finite impulse response (FIR) filter function and an infinite impulse response (IIR) filter function.