| 摘要 |
<p>In an information processing apparatus equipped with a cache memory, a TLB, and a TSB, when a TLB error occurs upon a memory access, the processing time of the memory access can be significantly reduced. The information processing apparatus comprises: a second search unit (14) for searching a second physical address from an address translation buffer means (13) by using a second virtual address having a one-to-one correspondence with a first virtual address; and a prefetch control unit (22) for registering a first address translation pair for the first virtual address from an address translation table (11) to a cache memory means (12) by using this searched second physical address.</p> |
