发明名称 Layout analysis method and apparatus for semiconductor integrated circuit
摘要 A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.
申请公布号 US2007106967(A1) 申请公布日期 2007.05.10
申请号 US20060396660 申请日期 2006.04.04
申请人 FUJITSU LIMITED 发明人 INOUE YOSHIO;YONEDA TAKASHI;ITO MASARU
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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