发明名称 METHOD AND DEVICE FOR ANALYZING INTEGRATED CIRCUITS
摘要 <p>The invention concerns a method for simulating an electronic circuit, comprising: a) defining, on the one hand, inputs and outputs of networks of the circuit and, on the other, internal components of each network; b) forming a reduced model of each network; c) simulating the network with the aid of this reduced model; d) in the event of an unsatisfactory result of the simulation, modifying one or a number of networks, forming a second reduced model, and simulating with this new reduced model; e) in the event of a satisfactory result of the simulation, manufacturing the circuit.</p>
申请公布号 WO2007051838(A1) 申请公布日期 2007.05.10
申请号 WO2006EP68074 申请日期 2006.11.03
申请人 S.A. EDXACT;GUEDON, STEPHANE 发明人 GUEDON, STEPHANE
分类号 G06F17/50 主分类号 G06F17/50
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