| 摘要 |
<p>The present invention relates to an improved semiconductor memory device providing row/column redundancy comprising a plurality of data latches (11) arranged in a row-column matrix connected to a set of bitlines / global bitlines interfacing to read/write circuitry, at least two redundant rows/columns (R1, R2) connected to a redundant bitline / global bitline, a first means (5) for providing a first faulty row/column address in the matrix, a second means (1, 16) for generating other faulty row/column addresses by incrementing or decrementing predetermined numbers from the address provided by the first means (5), a comparison circuitry (3, 13) receiving as its inputs the accessed row/column address and the faulty row/column addresses and a control block (4, 14) connected to the comparison circuitry (3, 13) and receiving a control signal (REN, CS) for normal operation of the memory device, the control block (4, 14) enabling/disabling the redundant rows/columns (R1, R2) and/or other memory cell rows/columns depending upon signals received from the comparison circuitry (3, 13) and the control signal (CS) for normal operation of the memory device.</p> |
