发明名称 Secure microprocessor with instructions verification
摘要 <p>The microprocessor (MIC) has an interface (INT) with a program memory (MEM) comprising instructions. Each instruction is composed of an opcode and operands. An instruction verification module (VER) includes a reading module (FE) to read an additional verification information defining a check value permitting to validate or invalidate the opcode part of the instruction. An interrupting unit interrupts the execution of the instruction if the opcode assumed during reading is invalid.</p>
申请公布号 EP1783648(A1) 申请公布日期 2007.05.09
申请号 EP20050109381 申请日期 2005.10.10
申请人 NAGRACARD S.A. 发明人 KUDELSKI, ANDRE
分类号 G06F21/52 主分类号 G06F21/52
代理机构 代理人
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