| 摘要 |
<p>Write in of lower significant bits of a digital video signal to a memory is eliminated by a memory controller of a signal control circuit in a display device during a second display mode in which the number of gray scales is reduced, as compared to a first display mode. Further, read out of the lower significant bits of the digital video signal from the memory is also eliminated. The amount of information of digital image signals input to a source signal line driver circuit is reduced. Corresponding to this operation, a display controller functions to make start pulses and clock pulses input to each driver circuit have a lower frequency, and write in periods and display periods of sub-frame periods participating in display are set longer.
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