发明名称 |
ADAPTIVE INPUT LOGIC FOR PHASE ADJUSTMENTS |
摘要 |
Systems and methods are disclosed to provide static and/or dynamic phase adjustments to a data signal relative to a clock signal. For example, the data signal may be delayed by a coarse delay and/or a fine delay to match the timing of the clock signal independently for each input path (e.g., per input pad). The delay may be as a function of positive and/or negative clock edges. |
申请公布号 |
EP1593199(A4) |
申请公布日期 |
2007.05.09 |
申请号 |
EP20040703082 |
申请日期 |
2004.01.16 |
申请人 |
LATTICE SEMICONDUCTOR CORPORATION |
发明人 |
ANDREWS, WILLIAM;SCHOLZ, HAROLD;BRITTON, BARRY |
分类号 |
H03H11/26;H03K5/00;H03K5/13;H03L7/081;H04B;H04L7/033 |
主分类号 |
H03H11/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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