Information processor and multi-hit control method

摘要

The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer (31) for storing address translation pairs and thread information, a retriever (32) for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer (31) for translating the virtual address into a physical address, a determination unit (34) for determining, when plural addresses translation pairs are retrieved by the retriever (32) , whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller (35) for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit (34).