发明名称 |
Address latch circuit of memory device |
摘要 |
An address latch circuit of a memory device is disclosed. A latch operation is disabled while an address signal makes a level transition in the memory device, and then enabled when the address signal is stabilized after the level transition. Therefore, it is possible to reduce power consumption caused during the level transition of the address signal.
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申请公布号 |
US7215594(B2) |
申请公布日期 |
2007.05.08 |
申请号 |
US20040980350 |
申请日期 |
2004.11.03 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
IM JAE-HYUK;KIM KYOUNG-NAM |
分类号 |
G11C8/00;G11C11/408;G11C5/06;G11C7/10;H03K3/12 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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