发明名称 |
Method and apparatus for model-order reduction and sensitivity analysis |
摘要 |
Computer time for modeling VLSI interconnection circuits is reduced by using symmetric properties of modified nodal analysis formulation. The modeling uses modified nodal analysis matrices then applies a Krylov subspace matrix to construct a congruence transformation matrix to generate the reduced order model of the VLSI.
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申请公布号 |
US7216309(B2) |
申请公布日期 |
2007.05.08 |
申请号 |
US20040839953 |
申请日期 |
2004.05.06 |
申请人 |
CHANG GUNG UNIVERSITY |
发明人 |
LEE HERNG-JER;CHU CHIA-CHI;FENG WU-SHIUNG |
分类号 |
G06F17/50;G06F17/00;G06F17/16;G06F17/17;G06F19/00 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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