发明名称 Edge incremental redundancy memory structure and memory management
摘要 A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes at least one processing device, an IR processing function, and IR memory. The at least one processing device is operable to receive analog signals corresponding to a data block, to sample the analog signals to produce samples, to equalize the samples to produce soft decision bits corresponding to the data block, and to initiate IR operations. The IR processing function is operable to perform IR operations on the soft decision bits of the data block in an attempt to correctly decode the data block. The IR memory operably couples to the IR processing function, includes Type I IR memory adapted to store IR status information of the data block, and includes Type II IR memory adapted to store the data block.
申请公布号 US7272768(B2) 申请公布日期 2007.09.18
申请号 US20030731804 申请日期 2003.12.09
申请人 BROADCOM CORPORATION 发明人 CHANG LI FUNG;WANG YONGQIAN
分类号 H03M13/00;H04B1/10;H04L1/00;H04L1/18;H04L1/20;H04L25/03;H04L25/06;H04L27/00 主分类号 H03M13/00
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