发明名称 |
Semiconductor device and semiconductor integrated circuit device |
摘要 |
Soft-error resistance and latch up resistance are simultaneously improved for LSI involving miniaturization and reducing operating voltage. P wells and N wells are formed in a higher density substrate (P on P+ substrate), and buried N wells are formed on a layer underlying thereof. A PMOSFET is formed in the N well and a NMOSFET is formed in the P well. A P well electric potential junction for coupling P well electric potential of the P well to predetermined electric potential is provided, and a region directly under the P well electric potential junction is provided with a region where the aforementioned buried N well is not disposed. The soft-error resistance is improved by having the buried N well therein, and the latch up resistance is improved by coupling the P well to the substrate. |
申请公布号 |
US7214989(B2) |
申请公布日期 |
2007.05.08 |
申请号 |
US20040975956 |
申请日期 |
2004.10.29 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
USHIRODA MASARU;FURUTA HIROSHI |
分类号 |
H01L27/04;H01L29/94;H01L21/822;H01L21/8238;H01L21/8239;H01L21/8244;H01L27/08;H01L27/092;H01L27/10;H01L27/105;H01L27/11;H01L29/76 |
主分类号 |
H01L27/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|