发明名称 |
Error portion detecting method and layout method for semiconductor integrated circuit |
摘要 |
For the purpose of readily specifying a portion of the circuit which has a high possibility of error occurring due to a variation in the supply voltage so that the specified vulnerable portion is countermeasured in a mask layout process, a simulation section simulates the operation of a semiconductor integrated circuit to obtain a transition timing of an input signal that is input to each circuit element. A simultaneous-operation circuit element number detecting section detects, based on a result of the simulation, the number of circuit elements which are supplied with the supply voltage through a common power supply line and in which transition timings of input signals occur within a predetermined time interval (e.g., 0.3 ns or shorter). A supply voltage variation level estimating section estimates the variation level of the supply voltage according to the number of circuit elements which is detected by the simultaneous-operation circuit element number detecting section.
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申请公布号 |
US7216315(B2) |
申请公布日期 |
2007.05.08 |
申请号 |
US20040751523 |
申请日期 |
2004.01.06 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
YOSHIDA TAKAKI |
分类号 |
G06F17/50;G01R29/02;G01R29/26;G01R31/02;G01R31/28;H01L21/82;H01L21/822;H01L27/04;H02H3/05 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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