发明名称 |
Semiconductor memory system having multiple system data buses |
摘要 |
The semiconductor memory system includes a memory controller, N system data buses, and first through P-th memory module groups. The N system data buses are connected to the memory controller and respectively have a width of M/N bits. The first through P-th memory module groups are connected to the N system data buses and respectively have N memory modules. In each of the first through P-th memory module groups, a different one of the N system data buses is connected to each of the N memory modules, and each of the N system data buses has a data bus width of M/N bits. The first through P-th memory module groups are operated in response to first through P-th corresponding chip select signals. M is the bit-width of an entire system data bus of the semiconductor memory system. The N system data buses are wired such that data transmission times are the same from each N memory modules that operate in response to the same chip select signal to the memory controller.
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申请公布号 |
US7215561(B2) |
申请公布日期 |
2007.05.08 |
申请号 |
US20030644735 |
申请日期 |
2003.08.21 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
PARK MYUN-JOO;SO BYUNG-SE;LEE JAE-JUN |
分类号 |
G06F13/16;G11C5/00;G06F13/42;G11C8/00 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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