发明名称 |
Method of HDL simulation considering hard macro core with negative setup/hold time |
摘要 |
A method of HDL simulation is described, which may enhance HDL simulation accuracy by allowing a simulator to process a negative setup time and/or hold time. For an electronic circuit device negative setup time and/or a negative hold time, a simulation may be executed without altering the negative setup time and/or hold time to be interpreted as zero. A setup time and/or hold time may be negative relative to a particular clock cycle while being positive relative to another clock cycle. Incorporating the value of the negative setup time and/or hold time without altering its value to zero may increase the accuracy of HDL simulations.
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申请公布号 |
US7213222(B2) |
申请公布日期 |
2007.05.01 |
申请号 |
US20040867726 |
申请日期 |
2004.06.16 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JANG MI-SOOK;LEE HOI-JIN |
分类号 |
G06F17/50;G06F9/45;G06G7/62;H01L21/82 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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