| 摘要 |
The present invention relates to a semiconductor circuit; and, more particularly, to a duty cycle correction circuit (hereinafter referred to as "DCC"). Furthermore, the present invention relates to an open-loop digital DCC. The duty cycle correction circuit according to the present invention includes: a delayer for delaying an input clock signal and for generating a plurality of delayed clock; a phase comparator for comparing the input clock signal with the plurality of delayed clock signals; a multiplexer for selecting one out of the delayed clock signals in response to an output signal of the phase comparator and for inverting the selected delay clock signals; and a phase combiner for combining the clock signal from the multiplexer and the input clock signal. Accordingly, the digital DCC according to the present invention is of an open loop without any DLL, the duty correction can be made within five clock periods after power-up.
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