发明名称 |
Jitter suppressing delay locked loop circuits and related methods |
摘要 |
Delay locked loop circuits are provided that include a delay locked loop that generates a delay locked loop output signal and a jitter suppressor. The jitter suppressor may comprise a delay circuit that receives the delay locked loop output signal and generates one or more delayed versions of the delay locked loop output signal and a phase interpolator that receives the delay locked loop output signal and the one or more delayed versions of the delay locked loop output signal. In certain embodiments of the present invention, the delay circuit may comprise a plurality of serially connected delay cells. Each of these delay cells may delay signals input thereto for at time equal to one clock period of an external clock signal that is input to the delay locked loop.
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申请公布号 |
US7212052(B2) |
申请公布日期 |
2007.05.01 |
申请号 |
US20040925522 |
申请日期 |
2004.08.25 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM KYU-HYOUN |
分类号 |
H03L7/06;G11C11/407;H03L7/081;H03L7/10 |
主分类号 |
H03L7/06 |
代理机构 |
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主权项 |
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