| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve a write margin of a memory cell in a semiconductor memory composed of the memory cells having complementary storage nodes. <P>SOLUTION: Each memory cell has a pair of inverters INV3-4, the input/output of which are connected each other, and respectively hold complementary data on the storage nodes ND1-2 output from the inverters INV3-4. A power source voltage VDDL of the inverter INV3 having the storage node ND1 to which a low level is written, is set to be lower than a power source voltage VDDR of the inverter INV4 having the storage node ND2 to which a high level is written, by a power source control circuit PCNT during a writing operation that the complementary data are written respectively in the storage nodes ND1-2. Since a power supply ability to the inverter INV3 having the storage node ND1 to which the low level is written, is decreased, a voltage of the storage node ND1 is easily changed to the low level. That is, the writing margin of the memory cell MC can be improved. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
