发明名称 SYSTEM AND METHOD FOR MEMORY ARRAY ACCESS WITH FAST ADDRESS DECODER
摘要 A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
申请公布号 US2007094480(A1) 申请公布日期 2007.04.26
申请号 US20060552817 申请日期 2006.10.25
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 RAMARAJU RAVINDRARAJ;BEARDEN DAVID R.;KENKARE PRASHANT U.
分类号 G06F9/34 主分类号 G06F9/34
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