| 摘要 |
PROBLEM TO BE SOLVED: To avoid a failure in clock timing, supplied to place a switched capacitor circuit in operation, due to variance, parasitic resistance and capacity that a wire has, etc., when the switched capacitor circuit is made fast. SOLUTION: A bottom plate sampling period and a non-overlap period of the clock signal supplied to place the switched capacitor circuit in operation are made adjustable in timing by a control means to avoid a timing failure and a clock signal generating circuit can be constituted without increasing the area of a logic circuit determining the respective periods. COPYRIGHT: (C)2007,JPO&INPIT
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