| 摘要 |
A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for detecting a phase error from sampling data and the sampling clock, the sampling data being sampled from the input data at timing of the sampling clock; frequency error detection means for detecting, based on a differential coefficient obtained as a result of detecting the phase error, a frequency error; and frequency correction means for correcting a frequency of the sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of the PLL circuit, the frequency correction value being calculated based on the frequency error.
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