发明名称 MEMORY REDUNDANCY PROGRAMMING
摘要 A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes a charge trapping area. A threshold voltage of the access transistor is modified upon trapping of charges in the charge trapping unit. The memory device also includes a memory element and a fuse associated with the memory element. The fuse is capable of entering an alternative state in response to modifying the threshold voltage of the access transistor. The state of the fuse may be used to program or de-program the memory element.
申请公布号 US2007091706(A1) 申请公布日期 2007.04.26
申请号 US20060565439 申请日期 2006.11.30
申请人 发明人 PAREKH KUNAL R.
分类号 G11C17/18 主分类号 G11C17/18
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