发明名称 Using hardware transactional memory for implementation of queue operations
摘要 Using hardware transactional memory (HTM) for queue operations includes invoking a first operation for a concurrent linked queue of an interpretive program using a Just-In-Time (JIT) compiler of a virtual machine, wherein the first operation does not use HTM, determining whether a data processing system executing the virtual machine supports HTM, and responsive to determining that the data processing system does support HTM, detecting, using a processor and within the first operation, a call to a second operation that is that is configured, in byte code, to return an indication of a failed hardware transaction. Responsive to detecting the second operation, a machine code implementation of the first operation that includes a machine code implementation of the second operation is generated. The machine code implementation of the second operation is an implementation of the first operation that does use HTM.
申请公布号 US9348621(B2) 申请公布日期 2016.05.24
申请号 US201313906674 申请日期 2013.05.31
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Michael Maged M.;Zheng Jing Ru
分类号 G06F9/45;G06F9/455;G06F9/44;G06F9/52;G06F9/46 主分类号 G06F9/45
代理机构 Cuenot, Forsythe & Kim, LLC 代理人 Cuenot, Forsythe & Kim, LLC
主权项 1. A method, comprising: invoking a first operation for a concurrent linked queue of an interpretive program using a Just-In-Time (JIT) compiler of a virtual machine, wherein the first operation does not use hardware transactional memory; determining whether a data processing system executing the virtual machine supports hardware transactional memory; responsive to determining that the data processing system does support hardware transactional memory, detecting, using a processor and within the first operation, a call to a second operation that is configured, in byte code, to return an indication of a failed hardware transaction; and responsive to detecting the second operation, generating a machine code implementation of the first operation that includes a machine code implementation of the second operation, wherein the machine code implementation of the second operation is an implementation of the first operation that does use hardware transactional memory in lieu of machine code for the byte code of the second operation that returns the indication of the failed hardware transaction.
地址 Armonk NY US