Stitchable global clock for 3D chips

摘要

A stitchable clock mesh, a dual operation mode method, and a master clock stratum are provided for a 3D chip stack. The stitchable clock mesh includes at least one clock mesh, on each of the two or more strata, having a plurality of sectors for providing a global clock signal. The stitchable clock mesh further includes mesh data sensors, on each of the two or more strata, for collecting mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The stitchable clock mesh further includes mesh segmentation and joining circuitry for selectively performing a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.

主权项

1. A stitchable clock mesh for a 3D chip stack having two or more strata, comprising:
at least one clock mesh, on each of the two or more strata, having a plurality of sectors for providing a global clock signal to various chip locations; mesh data sensors, on each of the two or more strata, for collecting mesh data for the at least one mesh, the mesh data including measured functional data and measured performance data for a current system configuration; and mesh segmentation and joining circuitry for selectively performing a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.