| 摘要 |
A ferroelectric memory device including a pair of main bit lines (MBLU 1 , MBLL 1 ) having generally identical line width and line length, a sense amplifier (SA) that lies between one of the main bit lines and the other of the main bit lines, a plurality of local bit lines (LBLU 1 , etc.) associated with each of the main bit lines, a plurality of switching elements (TrU 1 , etc.), each provided between each of the local bit lines and the main bit line, a plurality of memory cells (MCU 1 , etc.), and a plurality of dummy cells (DMC 1 , etc.) for generating a reference potential, wherein one of the main bit lines is connected to one of the local bit lines to readout data from one of the memory cells connected to the one of the local bit lines, and the dummy cell connected to the other of the main bit lines is selected to generate a reference potential.
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