| 摘要 |
Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large memory arrays the leakage current is a considerable portion of the overall power consumption, leakage reduction in memory arrays, manufactured by advanced processing technologies, is a major challenge. To reduce leakage, methods and apparatus are presented for memory access and for power- and ground-supply monitoring and management at memory sub-array level.
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