发明名称 Flash Channel with Selective Decoder Likelihood Dampening
摘要 An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.
申请公布号 US2016246674(A1) 申请公布日期 2016.08.25
申请号 US201514928941 申请日期 2015.10.30
申请人 Seagate Technology LLC 发明人 Chen Zhengang;Wu Yunxiang;Alhussien AbdelHakim S.;Haratsch Erich F.
分类号 G06F11/10;H03M13/11;G11C29/52 主分类号 G06F11/10
代理机构 代理人
主权项 1. A device comprising: a digital read channel circuit including: a circuit configured to map received data patterns to likelihood values;a decoder configured to decode the likelihood values;a control circuit configured to: select at least one dampening candidate from the likelihood values that failed decoding;dampen the at least one dampening candidate to generate dampened likelihood values; andthe decoder configured to decode the dampened likelihood values to output decoded data.
地址 Cupertino CA US