发明名称 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
摘要 An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.
申请公布号 US2016246597(A1) 申请公布日期 2016.08.25
申请号 US201615145748 申请日期 2016.05.03
申请人 Ben-Kiki Oren;Pardo llan;Valentine Robert;Weissmann Eliezer;Markovich Dror;Yosef Yuval 发明人 Ben-Kiki Oren;Pardo llan;Valentine Robert;Weissmann Eliezer;Markovich Dror;Yosef Yuval
分类号 G06F9/30 主分类号 G06F9/30
代理机构 代理人
主权项 1. A processor comprising: execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying one or more commands, the command data to be read by one or more accelerators; the command data to be read by one or more accelerators which are to responsively attempt to execute the one or more commands identified by the command data; and an accelerator context save/restore pointer to identify a region within system memory where the accelerator is to save its state upon a switch from a first context to a second context and to later restore its state upon returning to the first context.
地址 Tel-Aviv IL