Method of forming a CMOS-based thermoelectric device

摘要

An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

主权项

1. A method of forming an integrated circuit, the method comprising:
providing a substrate including silicon-based semiconductor material; forming isolation trenches in the substrate between active areas of the integrated circuit to laterally isolate active areas for an NMOS transistor and a PMOS transistor in an area for CMOS transistors of the integrated circuit, and for n-type thermoelectric elements and p-type thermoelectric elements of an embedded thermoelectric device of the integrated circuit, the n-type thermoelectric elements and the p-type thermoelectric elements being less than 300 nanometers wide at a narrowest position; subsequently implanting n-type dopants into the substrate to form an n-type region having a doping density of at least 1×1018 cm−3 which encompasses the n-type thermoelectric elements and the substrate between the n-type thermoelectric elements at least 100 nanometers below the isolation trenches, and implanting p-type dopants into the substrate to form a p-type region having a doping density of at least 1×1018 cm−3 which encompasses the p-type thermoelectric elements and the substrate between the p-type thermoelectric elements at least 100 nanometers below the isolation trenches; subsequently forming dielectric material in the isolation trenches to provide field oxide of the integrated circuit; and forming a metal interconnect structure which connects upper ends of the n-type thermoelectric elements and the p-type thermoelectric elements to a thermal node.