发明名称 Semiconductor device having buried gate structure and method of fabricating the same
摘要 A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.
申请公布号 US9437697(B2) 申请公布日期 2016.09.06
申请号 US201414551857 申请日期 2014.11.24
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Cho Min-Hee
分类号 H01L29/423;H01L29/78;H01L29/49 主分类号 H01L29/423
代理机构 F. Chau & Associates, LLC 代理人 F. Chau & Associates, LLC
主权项 1. A semiconductor device, comprising: a device isolation region defining an active region in a substrate; and gate structures buried in the active region of the substrate, wherein at least one of the gate structures comprises: a gate trench; a gate insulating layer formed on an inner wall of the gate trench; a gate barrier pattern formed on the gate insulating layer disposed on a lower portion of the gate trench; a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench; an electrode protection layer formed on the gate insulating layer disposed on an upper portion of the gate trench and contacting the gate electrode pattern, wherein a bottom surface of the electrode protection layer is in contact with an upper surface of the gate barrier pattern and wherein a portion of the electrode protection layer is disposed between the gate insulating layer and the gate electrode pattern; a buffer oxide layer formed on the electrode protection layer; and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench, wherein the buffer oxide layer is U-shaped, and wherein a bottom and side surfaces of the gate capping insulating layer are covered by the buffer oxide layer.
地址 Suwon-Si, Gyeonggi-Do KR