发明名称
摘要 <p>A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.</p>
申请公布号 JP3905928(B2) 申请公布日期 2007.04.18
申请号 JP19930237310 申请日期 1993.08.31
申请人 发明人
分类号 G06F15/78;G06F1/00;G06F9/30;G06F9/445;G06F11/00;G06F21/00 主分类号 G06F15/78
代理机构 代理人
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