发明名称
摘要 <P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which performs stable reading-out with little degradation and easily improves integration degree. <P>SOLUTION: The semiconductor memory device is provided with a volatile latch circuit SRAM which holds data, a nonvolatile ferroelectric capacitor circuit NVC which holds data, and a switching circuit SW which cuts and connects the latch circuit SRAM and the ferroelectric capacitor circuit NVC. The switching circuit SW is connected only when inputting and outputting data between the latch circuit SRAM and the ferroelectric capacitor circuit NVC. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP3907664(B2) 申请公布日期 2007.04.18
申请号 JP20050047968 申请日期 2005.02.23
申请人 发明人
分类号 G11C11/41;H03K19/177;G11C11/22 主分类号 G11C11/41
代理机构 代理人
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