| 摘要 |
<P>PROBLEM TO BE SOLVED: To enhance processing speed by simplifying circuit structure of a synchronizing circuit more. <P>SOLUTION: In the synchronizing circuit 10, inversion/non-inversion of a clock to be inputted in a bit string acquisition part 18 is switched based on a bit pattern of a bit string acquired by the bit string acquisition part 18. Since the bit string acquisition part 18 performs sampling and bit shift on any one of rise or fall of the clock (CK) to be inputted, when the clock is inverted, sampling timing, consequently, reference timing of the synchronizing circuit 10 changes. Since such a structure simplifies the circuit structure in comparison with the conventional device which changes a cycle or a frequency of the clock, smaller and higher speed synchronizing circuit is obtained. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
