发明名称 |
High reliability memory subsystem using data error correcting code symbol sliced command repowering |
摘要 |
A memory subsystem comprising: a command register in operable communication with a plurality of memory devices via a plurality of command buses. The plurality of memory devices is arranged into symbol slices and each symbol slice is configured to be part of a single error correction code packet. Each command bus of the plurality of command buses is configured to interface between the command register and each memory device in a particular symbol slice. A method of command bus redundancy comprising: configuring a plurality of memory devices into symbol slices, each symbol slice configured to be part of a single error correction code packet; establishing a plurality of command buses, each command bus configured to interface with each memory device in a particular symbol slice; and configuring a command register with sufficient command bus drivers to support each command bus of the plurality of command buses.
|
申请公布号 |
US7206962(B2) |
申请公布日期 |
2007.04.17 |
申请号 |
US20030723055 |
申请日期 |
2003.11.25 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DEEGAN JOHN M.;GOWER KEVIN CHARLES |
分类号 |
G06F11/10;G06F13/42;G11C29/00 |
主分类号 |
G06F11/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|