| 发明名称 |
Semiconductor device layout method, a computer program, and a semiconductor device manufacture method |
| 摘要 |
A semiconductor device layout method is disclosed, wherein vias carrying the same signal are arranged at intervals equal to the minimum value defined by a design rule, and vias carrying different signals are arranged at second intervals that are greater than the minimum value.
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| 申请公布号 |
US7207023(B2) |
申请公布日期 |
2007.04.17 |
| 申请号 |
US20040861260 |
申请日期 |
2004.06.04 |
| 申请人 |
RICOH COMPANY, LTD. |
发明人 |
YOSHIOKA KEIICHI |
| 分类号 |
G06F17/50;H01L21/3205;G06F9/45;H01L21/768;H01L21/82;H01L23/52;H01L23/522 |
主分类号 |
G06F17/50 |
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