Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic

摘要

A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry signals. In a method for producing a carry logic circuit, a group generate logic function G_{I, I+1}=G_I OR G_I+1 AND P_I is to be performed. When G_I+1=C_I+1, G_{I, I+1}=C_I, arrival times of generate signals G_I and G_I+1, are investigated. If G_I arrives before G_I+1, a complex AND-OR-INVERT gate is used, otherwise a cascaded pair of NAND gates is selected. To produce a complementary carry signal, a logic function G_{I, I+1}'=G_I' AND G_I+1' OR P_I' is to be performed. If the generate signal G_I' arrives before G_I+1', a complex OR-AND-INVERT gate is used, otherwise a cascaded pair of NOR gates is selected.