发明名称 Modular multiplication method and calculating device
摘要 To provide a modular multiplication method and a calculating device that do not rely on the Montgomery technique, wherein the number of times of multiply-add calculations is reduced to shorten a calculation time for calculation speed-up, there is no limitation in input value, and it is possible to execute a remainder calculation exceeding the calculable maximum bit length of a multiply-add unit that is used. Assuming that N=2<SUP>n</SUP>-M and X=alphax2<SUP>n</SUP>+beta, a relation of XmodN=(alphaxM+beta)modN is derived, which is utilized. n represents a maximum bit number where "1" is assigned in N, a solution of 2<SUP>n+1</SUP>modN is set as b, AxB is set as X, XmodN is transferred to (X/2<SUP>n+1</SUP>xb+Xmod2<SUP>n+1</SUP>)modN and further transferred to (X.n/2<SUP>n+1</SUP>xb+X.nmod2<SUP>n+1</SUP>)modN, calculations of X.n/2<SUP>n+1</SUP>xb+X.nmod2<SUP>n+1 </SUP>are repeated until a bit length of X.n becomes n+1, X.n-N is derived and a derived result is set as a solution of "AxBmodN".
申请公布号 US7206799(B2) 申请公布日期 2007.04.17
申请号 US20020282107 申请日期 2002.10.29
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 YAMAZAKI HIROSHI
分类号 G06F7/38;G06F7/72;G06F7/52;G09C1/00;H04K1/00 主分类号 G06F7/38
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