发明名称 METHOD FOR FORMING TRENCH ISOLATION STRUCTURE IN INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To improve the reliability of an integration circuit which is manufactured with trench isolation by forming a trench isolation structure with a void-free trench plug 36 equipped thereto. SOLUTION: A polysilicon layer 28 is formed in a trench 22 and then subsequently oxidized to form a first dielectric layer 30. The first dielectric layer 30 is then etched and a second dielectric layer 34 is subsequently formed over an etched dielectric layer 32. A portion of the second dielectric layer 34 is then removed using chemical-mechanical polishing to form a void-free trench plug 36 in the trench 22. In addition, the subsequent etching of the trench plug 36 after the trench plug 36 has been formed is minimized. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007096353(A) 申请公布日期 2007.04.12
申请号 JP20070001007 申请日期 2007.01.09
申请人 FREESCALE SEMICONDUCTOR INC 发明人 PERERA ASANGA H
分类号 H01L21/76;H01L21/762 主分类号 H01L21/76
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