| 摘要 |
PROBLEM TO BE SOLVED: To provide an internal address generator for reducing current consumption. SOLUTION: The internal address generator includes: a read address generation means for generating an external address as a plurality of AL delay addresses with delay on the basis of an additive drive clock and outputting a signal corresponding to set additive latency as an additive address; a write address generation means for generating the additive address as a plurality of CL delay addresses with delay time on the basis of a CAS drive clock and outputting a signal corresponding to set CAS latency as a write address; a drive clock generation means for outputting an internal clock as the additive drive clock or the CAS drive clock in response to a write section signal to be active at the time of the additive latency and write drive; and an output means for outputting the additive address or the write address as an internal column address in response to the write section signal. COPYRIGHT: (C)2007,JPO&INPIT
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